Field effect transistor

ABSTRACT

A dielectric film  4  made of a high dielectric material with a relative permittivity of 8 or more is laid between a field plate section  9  and a channel layer  2 . Tantalum oxide (Ta 2 O 5 ), for example, may be used as the high dielectric material.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a Schottky gate field effecttransistor (FET) that operates in the microwave region used for mobilecommunication, satellite communication, satellite broadcasting and thelike.

[0003] 2. Description of the Prior Art

[0004] In comparison with Si, compound semiconductors are known to havehigh electron mobilities. For example, the electron velocity of GaAs isapproximately 6 times in the low electric field and 2 to 3 times in thehigh electric field as fast as that of Si. Such characteristics ofhigh-speed electrons have been put to a good use in developingapplications thereof to high-speed digital circuit elements orhigh-frequency analog circuit elements.

[0005] In an FET using a compound semiconductor, however, a gateelectrode makes a Schottky junction with a channel layer of a substrateso that the electric field centers on a lower end (a circledfield-centered section in FIG. 14) of the gate electrode on the drainside, which may cause breakdown. This is the matter of great concern,especially for a high-output FET that necessitates large signaloperations.

[0006] Accordingly, several attempts have been hitherto made to preventthis field centralization on the edge section of the gate electrode onthe drain side and improve characteristics of withstand voltage.

[0007] Among them, there is one attempt in which an overhanging section(referred to as a ‘field plate section’, hereinafter) is set in a gateelectrode, and, under this, a dielectric film made of SiO₂ is formed.FIG. 12 shows schematically the structure of the FET disclosed inJapanese Patent Application Laid-open No. 87773/1988, wherein adielectric film 34 is buried in a section below a gate electrode 33 onthe drain side. Such a dielectric film, if set, is generally consideredto be able to suppress the field centralization on the edge section ofthe gate electrode 33 on the drain side.

[0008] In the above-mentioned conventional techniques, however, thedielectric film must be made thin for the purpose of obtaining asufficient effect on the field relaxation so that the value ofelectrostatic capacitance of a capacitor that consists of a field platesection and a channel layer separated by the dielectric film becomeslarge. On the other hand, the reduction in the thickness of thedielectric film tends to lead to a problem that the breakdown of thedielectric film or the leakage of the current may take place.

[0009] Further, because there is a certain limit in making thedielectric film thin, the maximum value for the electrostaticcapacitance naturally exists. Therefore, to attain a sufficient effecton the field relaxation, the length of the field plate section should bemore than a certain length, for example, a gate length, which may causea problem of lowering the gain characteristics. Moreover, in thisinstance, high-frequency characteristics worsen significantly and thismay become a crucial problem, depending on the purpose of use thereof.

SUMMARY OF THE INVENTION

[0010] Accordingly, an object of the present invention is to overcomethe above-mentioned problems associated with the prior art and providean FET having high withstand voltage characteristics and good gaincharacteristics, together with excellent high-frequency characteristics.

[0011] In light of the above problems, the present invention provides anFET; comprising:

[0012] a semiconductor substrate with a channel layer being formed onits surface;

[0013] a source electrode and a drain electrode being formed at adistance on said semiconductor substrate; and

[0014] a gate electrode being placed between said source electrode andsaid drain electrode and making a Schottky junction with said channellayer; wherein:

[0015] said gate electrode is provided with an overhanging field platesection; and

[0016] between said field plate section and said channel layer, there islaid a dielectric film made of a high dielectric material with arelative permittivity of 8 or more.

[0017] In the FET of the present invention, because a dielectric film islaid between the field plate section and the channel layer, the fieldcentralization which develops on the edge section of the gate electrodeon the drain side is made to relax and spread over, improvingcharacteristics of withstand voltage. This results from a fact that acapacitor that consists of the field plate section and the channel layerseparated by the dielectric film has a function to end the electric fluxline starting from ionized donors.

[0018] In the FET of the present invention, as a material for thedielectric film laid between the field plate section and the channellayer, a material with a relative permittivity of 8 or more is utilized.Therefore, even when the dielectric film is made thick, a highelectrostatic capacitance can be obtained and, in consequence, asufficient effect on the field relaxation can be attained. For example,compared with a SiO₂ film being used in the prior art, the filmthickness can be made about twice as much as the conventional thicknessto obtain the same given electrostatic capacitance.

[0019] As described above, since the film thickness of the dielectricfilm in the present invention can be made greater than the conventionalone, the breakdown of the dielectric film and the generation of theleakage current can be prevented and characteristics of withstandvoltage of element can be improved.

[0020] Further, because the dielectric film with a high permittivity islaid therein, as mentioned above, even if the length of the field platesection is not very long, a sufficient effect on the field relaxationcan be attained. For instance, the length of the field plate section canbe shorter than the gate length. Therefore, high withstand voltagecharacteristics can be obtained, while the reduction of the gaincharacteristics is kept down.

[0021] Further, the present invention provides an FET; comprising:

[0022] a semiconductor substrate with a channel layer being formed onits surface;

[0023] a source electrode and a drain electrode being formed at adistance on said semiconductor substrate; and

[0024] a gate electrode being placed between said source electrode andsaid drain electrode and making a Schottky junction with said channellayer; wherein:

[0025] said gate electrode is provided with an overhanging field platesection; and

[0026] between said field plate section and said channel layer, there islaid a dielectric film; and

[0027] when the relative permittivity and the film thickness of thedielectric film are denoted by ε and t (nm), respectively, one of thefollowing conditions (1) and (2) is satisfied.

(1) 1<ε<5, and 25<t/ε<70  (1)

5=ε<8, and 100 <t<350  (2)

[0028] In the prior art, it was difficult to achieve a sufficient effecton the field relaxation, while preventing the breakdown of thedielectric film directly under the field plate section and the leakageof the current at the same time.

[0029] The present invention attempts to overcome this, by looking intothe relative permittivity and the film thickness of the dielectric filmand defining the relation between there two.

[0030] When 1<ε<5 is satisfied, if t/ε is less than 25, the breakdown ofthe dielectric film or the leakage current takes place. On the otherhand, if t/ε exceeds 70, a sufficient effect on the field relaxationcannot be attained. The relative permittivity and the film thickness,hereat, mean the average values of the relative permittivity and thefilm thickness of the dielectric film directly under the field platesection, respectively. In the case that a plurality of dielectric filmsmade of different materials are laid directly under the field platesection, a reduced value (t/ε)_(RED) given by the following equation isused as the value of t/ε thereof,

(t/ε)_(RED) =t ₁/ε₁ +t ₂/ε₂ +. . . +t _(n)/ε_(n)

[0031] (n is an integer that is equal to or more than 2).

[0032] Further, when 5≦ε≦8 is satisfied, if t is less than 100, thebreakdown of the dielectric film or the leakage current takes place. Onthe other hand, if t exceeds 350, a sufficient effect on the fieldrelaxation cannot be attained. The film thickness, hereat, means theaverage value of the film thickness of the dielectric film directlyunder the field plate section.

[0033] As described above, in the FET of the present invention, adielectric film with a relative permittivity of 8 or more is formedbetween a field plate section of a gate electrode and a channel layer.The use of such a material with a high permittivity allows making thefilm thickness of the dielectric film substantial, while maintaining asufficient effect on the field relaxation. In consequence, the FET ofthe present invention is well protected against the breakdown of thedielectric film and the generation of the current leakage that are thevery problem for the prior art. Therefore, characteristics of withstandvoltage can be improved with effect while the reduction of the gaincharacteristics is kept down.

[0034] Further, in the FET of the present invention, because a materialhaving a certain relationship between the relative permittivity and thefilm thickness of the dielectric film is utilized as the material of thedielectric film, characteristics of withstand voltage can be improvedwith effect while the reduction of the gain characteristics is keptdown.

[0035] Further, with a structure in which the electrostatic capacitanceper unit area of a capacitor that consists of the field plate sectionand a channel layer separated by the dielectric film decreases withincreasing distance from the gate electrode, the effect on the fieldrelaxation due to the field plate section is moderated on the drainside, which facilitates to achieve an ideal field profile. Therefore,characteristics of withstand voltage can be improved with effect, whiledeterioration of high-frequency characteristics is kept down to theminimum.

[0036] Further, setting a field control electrode between the gateelectrode and the drain electrode brings about the multiplicationeffect, together with the effect on the field relaxation due to thefield plate section and further improves characteristics of withstandvoltage.

[0037] Further, the formation of a sub electrode between the gateelectrode and the source electrode can lead to achieve a higherefficiency of the element.

BRIEF DESCRIPTION OF THE DRAWINGS

[0038]FIG. 1 is schematic cross-sectional views illustrating in sequencethe steps of a manufacturing method of an FET in accordance with thepresent invention.

[0039]FIG. 2 is schematic cross-sectional views illustrating in sequencethe further steps of the manufacturing method of the FET in accordancewith the present invention.

[0040]FIG. 3 is schematic cross-sectional views illustrating in sequencethe steps of another manufacturing method of an FET in accordance withthe present invention.

[0041]FIG. 4 is schematic cross-sectional views illustrating in sequencethe steps of another manufacturing method of an FET in accordance withthe present invention.

[0042]FIG. 5 is schematic cross-sectional views illustrating in sequencethe further steps of the manufacturing method of the FET in accordancewith the present invention.

[0043]FIG. 6 is schematic cross-sectional views illustrating in sequencethe steps of a manufacturing method of another FET in accordance withthe present invention.

[0044]FIG. 7 is a schematic cross-sectional view showing the FET inaccordance with the present invention.

[0045]FIG. 8 is schematic cross-sectional views illustrating in sequencethe steps of another manufacturing method of an FET in accordance withthe present invention.

[0046]FIG. 9 is schematic cross-sectional views illustrating in sequencethe further steps of the manufacturing method of the FET in accordancewith the present invention.

[0047]FIG. 10 is a schematic cross-sectional view showing another FET inaccordance with the present invention, together with a group ofschematic top plan views showing various field plate sections thereof.

[0048]FIG. 11 is a pair of schematic cross-sectional views each showingan FET in accordance with the present invention.

[0049]FIG. 12 is a schematic cross-sectional view showing a conventionalFET.

[0050]FIG. 13 is a schematic cross-sectional view showing another FET inaccordance with the present invention.

[0051]FIG. 14 is a schematic cross-sectional view of a conventional FETin explaining the field centralization on a lower end of a gateelectrode therein.

[0052]FIG. 15 is schematic cross-sectional views illustrating insequence the steps of another manufacturing method of an FET inaccordance with the present invention.

[0053]FIG. 16 is schematic cross-sectional views illustrating insequence the further steps of the manufacturing method of the FET inaccordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0054] In the present invention, the high dielectric material ispreferably a material selected from the group consisting aluminium oxide(Al₂O₃), aluminium nitride, tantalum oxide (Ta₂O₅), strontium titanate(SrTiO₃), barium titanate (BaTiO₃), barium titanate strontium(Ba_(x)Sr_(1-x)TiO₃ (0<x<1)) and bismuth tantalate strontium(SrBi₂Ta₂O₉). The above materials are each well suited to be formed as afilm and besides, having a high relative permittivity of 8 or more,capable to provide a high electrostatic capacitance when laid in aregion below a gate electrode.

[0055] In the present invention, the dielectric film is preferablyformed only in a region directly under the field plate section. Forinstance, as shown in FIG. 3 (d), it is preferable that a dielectricfilm is set directly under a gate electrode 5 but not in the otherregion between a source electrode 7 and a drain electrode 8. In thismanner, an unnecessary increase in capacitance between the gate and thedrain can be avoided and a decrease in the gain, prevented.

[0056] In the case that the dielectric film is formed only in a regiondirectly under the field plate section as mentioned above, it ispreferable to make the structure of the FET in such a way that thesurface of a channel layer is partially or entirely covered with asilicon oxide film and the dielectric film is laid between this siliconoxide film and the field plate section. In such a structure, over thesilicon oxide film, the channel layer comes into contact with theoverlying semiconductor layers and this facilitates to prevent theimpairment of the device characteristics which is caused by thedeterioration of the interface characteristics.

[0057] The width of a field plate section in the present invention ispreferably 0.1 μm or more and still more preferably 0.1 to 2 μm. If thewidth of the field plate section is excessively small, characteristicsof withstand voltage obtained may not be sufficient. On the other hand,when the value of the width of the field plate section is too large,both the gain characteristics and the high-frequency characteristics mayworsen.

[0058] In the present invention, in using a high dielectric material forthe dielectric film, the average value of the thickness of thedielectric film is preferably 100-1500 nm, and more preferably 300-1000nm. If the dielectric film is too thick, the effect on the fieldrelaxation is reduced. On the other hand, the excessive thinness of thedielectric film may result in the breakdown of the dielectric film orthe leakage of the current. It is preferable that an appropriate valuein the above range is selected, according to the value of permittivityof the dielectric film. Further, if the dielectric film comprises layersof structure, the sum of the thicknesses of all layers is preferablywithin the above range.

[0059] In the FET of the present invention, the electrostaticcapacitance per unit area of a capacitor that consists of the fieldplate section and the channel layer separated by the dielectric film ispreferably larger on the side of the gate electrode than on the side ofthe drain electrode. This moderates the effect on the field relaxationby the field plate section on the drain side and facilitates to achievean ideal field profile. Such an arrangement, in particular, can controldeterioration of high-frequency characteristics with effect.

[0060] Now, the magnitude of the above-mentioned electrostaticcapacitance C is given by Equation (1).

C=εS/d  (1)

[0061] (C : the capacitance, ε: the permittivity, S: the area ofelectrode, d: the distance between electrodes) Therefore, as thestructure of the FET as described above, there can be consideredstructures in which one of the variables among the distance betweenelectrodes d, the area of the electrode S and the permittivity ε isvaried with distance from the gate electrode. The following is FETsrealized in this way.

[0062] (i) A Field Effect Transistor Wherein the Thickness of ADielectric Film Directly Under A Field Control Electrode is Less on theSide of a Gate Electrode than on the Side of a Drain Electrode.

[0063] In this structure, the change in the electrostatic capacitanceper unit area is achieved by varying the distance between electrodes d.

[0064] (ii) A Field Effect Transistor Wherein One or More Openings areFormed in a Field Plate Section.

[0065] In this structure, the change in the electrostatic capacitanceper unit area is achieved by varying the area of electrode S. An exampleof a field plate section in such a structure is shown in FIG. 10(c). Asshown in the drawing, the opening is preferably set in a part of thefield plate section on the side of a drain electrode. ‘An opening’ inthis structure is a hole made through the field plate section and mayhave any shape.

[0066] (iii) A Field Effect Transistor Wherein the Edge Section of aField Plate Section on the Side of a Drain Electrode is Comb-shaped.

[0067] In this structure, the change in the electrostatic capacitanceper unit area is achieved by varying the area of electrode S. The formreferred to as ‘comb-shaped’ herein is an intricate form the edgesection of the field plate section takes, for instance, in FIG. 10 (a)and (b). The examples shown in the drawings, however, are given toillustrate the invention and not to limit the scope of the invention andany intricate form the edge section takes may be used as long as theeffective area of the electrode is reduced on the side of the drainelectrode.

[0068] (iv) A Field effect Transistor Wherein the Permittivity of aDielectric Film Directly Under a Field Plate Section Decreases withDistance from a Gate Electrode.

[0069] In this structure, the change in the electrostatic capacitanceper unit area is achieved by varying the permittivity ε.

[0070] In the FET of the present invention, a float electrode may be setunder the field plate section. In this arrangement, electrons are keptin the float electrode even when the applied voltage to the field platesection is switched off and, in consequence, the field centralization onthe edge section of the gate electrode on the drain side is relaxed andspread over. As a material for the float electrode, tungsten silicide(WSi), aluminium, gold, titanium/platinum/gold or the like can beutilized. The float electrode itself can be formed, for instance, by amethod in which a metal film is applied to the entire surface by meansof vapour deposition and thereafter superfluous sections are removed byion milling with a photoresist serving as a mask.

[0071] In the FET of the present invention, a field control electrodemay be additionally formed over the dielectric film on said channellayer, between said gate electrode and said drain electrode. The fieldcontrol electrode has a function to end the electric flux line startingfrom ionized donors, and, therefore, makes the field centralizationwhich develops on the edge section of the gate electrode on the drainside relax and spread over, which improves characteristics of withstandvoltage. Together with the effect on the field relaxation due to thefield plate section, this brings about the multiplication effect andfurther improves characteristics of withstand voltage. If both adielectric film directly under the field plate section and a fieldcontrol electrode are set, an ideal field profile can be producedbetween the gate electrode and the drain electrode, which results in astill further improvement in the characteristics of withstand voltagewhile the deterioration of the gain characteristics or thehigh-frequency characteristics is kept down to the minimum.

[0072] With respect to the high dielectric material used for the fieldcontrol electrode, it is preferably a high dielectric material with arelative permittivity of 8 or more. For instance, any material selectedfrom the group consisting aluminium oxide (Al₂O₃), aluminium nitride(AlN), tantalum oxide (Ta₂O₅), strontium titanate (SrTiO₃), bariumtitanate (BaTiO₃), barium titanate strontium (Ba_(x)Sr_(1-x)TiO₃(0<x<1)) and bismuth tantalate strontium (SrBi₂Ta₂O₉) is preferablyutilized. Further, when the relative permittivity and the film thicknessof the dielectric film are denoted by ε and t, respectively, a materialsatisfying one of the following conditions (1) and (2) may be employed.

1<ε<5, and 25<t/ε<70  (1)

5≦ε<8, 100<t<350  (2)

[0073] With regard to the material for the field control electrode,tungsten silicide (WSi), aluminium, gold, titanium/platinum/gold or thelike can be utilized. The field control electrode itself can be formed,for instance, by a method in which a metal film is applied to the entiresurface by means of vapour deposition and thereafter superfluoussections are removed by ion milling with a photoresist serving as amask.

[0074] The field control electrode herein is preferably connected withthe gate electrode and kept at the same electric potential, though itmay be set independently at a different potential from that of the gateelectrode. In particular, by adjusting the voltage applied to the fieldcontrol electrode appropriately, an ideal field profile can be producedand the field centralization directly under the gate electrode can beprevented from developing and, thus, characteristics of withstandvoltage can be improved, while good gain characteristics andhigh-frequency characteristics are maintained.

[0075] Further, in the FET of the present invention, a sub electrode maybe additionally set over the dielectric film on said channel layer,between said gate electrode and said source electrode. This can lowerthe resistance of the region directly under the sub electrode andachieve higher efficiency of the element.

[0076] With regard to the material for the sub electrode, tungstensilicide (WSi), aluminium, gold, titanium/platinum/gold or the like canbe utilized. The sub electrode itself can be formed, for instance, by amethod in which a metal film is applied to the entire surface by meansof vapour deposition and thereafter superfluous sections are removed byion milling with a photoresist serving as a mask. The sub electrode isconnected, for example, with a drain electrode, to which a positivevoltage is applied. This lowers the resistance of the region directlyunder the sub electrode and eases the current flow therethrough so thathigher efficiency of the element can be achieved.

[0077] In the FET of the present invention, it is preferable that adistance between the gate electrode and the drain electrode is longerthan a distance between the gate electrode and the source electrode.This structure is often referred to as an offset structure and can relaxand spread over the field centralization on the edge section of the gateelectrode on the drain side more effectively. Moreover, frommanufacturing point of view, this structure has the advantage ofrelative easiness in forming the field plate section. Further, the FETof the present invention preferably has a recess structure, by which thefield centralization on the edge section of the gate electrode on thedrain side can be relaxed and spread over more effectively. A recessstructure hereat can be a multi-stage recess.

[0078] In the FET of the present invention, a group III-V compoundsemiconductor such as GaAs may be utilized as a material to constitute asubstrate or a channel layer. The group III-V compound semiconductorsinclude GaAs, AlGaAs, InP, GaInAsP and the like. Using a material of agroup III-V compound semiconductor, the high-speed high-output fieldeffect transistor can be produced.

EXAMPLES First Example

[0079] In the FET of the present example, as shown in FIG. 2(g), a gateelectrode 5 is provided with an overhanging field plate section 9 andbetween this field plate section 9 and a channel layer, a dielectricfilm 4 made of Ta₂O₅ is formed.

[0080] Referring to FIGS. 1 and 2, a manufacturing method of the FET ofthe present invention is described below.

[0081] First, upon a semi-insulating GaAs substrate 1, an N-type GaAschannel layer 2 (with a thickness of 230 nm) doped with 2×10¹⁷cm⁻³ Siand an N-type GaAs contact layer 3 (with a thickness of 150 nm) dopedwith 5×10¹⁷cm⁻³ Si are grown in succession by the MBE (Molecular BeamEpitaxy) method (FIG. 1(a)).

[0082] Next, using a resist (not shown in the drawing) as a mask, thechannel layer 2 and the contact layer 3 are etched by wet etching with asulfuric acid based or phosphoric acid based etchant so as to form arecess (FIG. 1 (b)).

[0083] A dielectric film 4 of Ta₂O₅ is then deposited to a thickness of300 nm over the entire surface by the CVD (Chemical Vapour Deposition)method (FIG. 1(c)). On this dielectric film 4, a resist (not shown inthe drawing) is formed and, using this as a mask, a portion of thedielectric film 4 where a gate electrode is to be formed is etched bydry etching with CHF₃ or SF₆. Next, using the dielectric film 4 as amask, a portion of the channel layer 2 where the gate electrode is to beformed is etched to a depth of 30 nm or so (FIG. 1 (d)).

[0084] Next, a 100 nm-thick WSi film, a 50 nm-thick TiN film, a 15nm-thick Pt film and a 400 nm-thick Au film are deposited, in thisorder, over the entire surface by sputtering, which forms a gate metalfilm 6 (FIG. 2(e)). After that, a photoresist is applied only to asection thereof where the gate electrode is to be formed, and the othersuperfluous section is removed by ion milling, and thereby a gateelectrode 5 is formed (FIG. 2 (f)).

[0085] Following this, the prescribed portions of the dielectric film 4are etched to expose the contact layer 3 and then an 8 nm-thick Ni film,a 50 nm-thick AuGe film and a 250 nm-thick Au film are successivelygrown in this order by vacuum deposition and thereby a source electrode7 and a drain electrode 8 are formed to accomplish an FET (FIG. 2 (g)).

[0086] In the FET of the present example, because Ta₂O₅ (with a relativepermittivity of approximately 20) is utilized as a material of thedielectric film 4 lying between the field plate section and the channellayer, it is possible to make the film thickness of the dielectric film4 substantial while maintaining a sufficient effect on the fieldrelaxation. Accordingly, the FET of the present example is wellprotected against the breakdown of the dielectric film or the generationof the current leakage, which is the very problem associated with theprior art.

[0087] Further, while Ta₂O₅ is employed as a material of the dielectricfilm 4 in the present example, any one among silicon nitride (Si₃N₄),aluminium oxide (Al₂O₃), strontium titanate (SrTiO₃), barium titanate(BaTiO₃), barium titanate strontium (Ba_(x)Sr_(1-x)TiO₃ (0<x<1)) andbismuth tantalate strontium (SrBi₂Ta₂O₉) can be utilized. At this, thevalue of film thickness thereof is specifically determined according tothe permittivity of the selected material. For instance, in the casethat aluminium oxide (Al₂O₃) is used, the film thickness is set to be150 to 300 nm.

[0088] Further, while the channel layer 2 and the contact layer 3 areformed by the MBE method in the present example, they can be formed bythe MOCVD (Metal Organic Chemical Vapour Deposition) method, instead.

Second Example

[0089] In the FET of the present example, as shown in FIG. 3(d), adielectric film 4 of Ta₂O₅ is formed only in a region directly under afield plate section. Referring to FIG. 3, a manufacturing method of anEET of the present example is described below.

[0090] First, in the same way as First example, upon a semi-insulatingGaAs substrate 1, a layered structure of an N-type GaAs channel layer 2,an N-type GaAs contact layer 3, a dielectric film 4 and a gate metalfilm 6 is formed (FIG. 3(a)). Next, a photoresist is applied only to asection thereof where a gate electrode is to be formed, and the othersuperfluous section is removed by ion milling, and thereby a gateelectrode 5 is formed (FIG. 3(b)). Following this, the dielectric film 4formed in the region other than the section where the gate electrode 5is formed is removed by etching (FIG. 3(c)). After that, an 8 nm-thickNi film, a 50 nm-thick AuGe film and a 250 nm-thick Au film aresuccessively grown in this order by vacuum deposition and thereby asource electrode 7 and a drain electrode 8 are formed to accomplish anFET (FIG. 3(d)).

[0091] In the FET of the present example, because the dielectric film 4made of Ta₂O₅ is formed only in the region directly under the fieldplate section, excellent gain characteristics can be obtained whilemaintaining withstand voltage characteristics.

Third Example

[0092] In the FET of the present example, as shown in FIG. 5(e), adielectric film 4 of Ta₂O₅ is formed into a stepped shape in a regiondirectly under a field plate section. Referring to FIGS. 4 and 5, amanufacturing method of an FET of the present example is describedbelow.

[0093] First, in the same way as First example, upon a semi-insulatingGaAs substrate 1, an N-type GaAs channel layer 2 and an N-type GaAscontact layer 3 are formed. Next, a dielectric film 4 of Ta₂O₅ is formedthereon (FIG. 4(a)). The film thickness of the dielectric film 4 is setto be 300 nm.

[0094] Following this, a photoresist (not shown in the drawing) isapplied to a region other than a section where a gate electrode is to beformed and the dielectric film 4 is dry etched (FIG. 4(b)). After thephotoresist is peeled off, a photoresist (not shown in the drawing) isagain applied thereto but in such a way that a width of the openingsection thereof is broader than the previous one and then the dielectricfilm 5 is dry etched (FIG. 4(c)). In this way, a stepped part instructure is shaped in the section where the gate electrode is to beformed.

[0095] Next, a 100 nm-thick WSi film, a 50 nm-thick TiN film, a 15nm-thick Pt film and a 400 nm-thick Au film are deposited, in thisorder, over the entire surface by sputtering, which forms a gate metalfilm 6. After that, by removing the superfluous section, a gateelectrode 5 is formed (FIG. 5(d)).

[0096] Next, the dielectric film 4 formed in the region other than thesection where the gate electrode 5 is formed is removed by etching.Subsequently, an 8 nm-thick Ni film, a 50 nm-thick AuGe film and a 250nm-thick Au film are successively grown in this order by vacuumdeposition and thereby a source electrode 7 and a drain electrode 8 areformed to accomplish an FET (FIG. 5(e)). The film thickness of thedielectric film 4 for the stepped part under the field plate section is150 nm in a thin-film section shown on the left side of the drawing and300 nm in a thick-film section on the right side.

[0097] In the present example, because the stepped dielectric film madeof Ta₂O₅ is formed in the region directly under the field plate section,the FET produced has excellent high-frequency characteristics, togetherwith high withstand voltage characteristics.

Fourth Example

[0098] As shown in FIG. 7, the FET of the present example has astructure wherein a gate electrode is provided with an overhanging fieldplate section and two sorts of dielectric films 4 a and 4 b are formedbetween this field plate section and a channel layer 2. The dielectricfilm 4 b has a lower relative permittivity than the dielectric film 4 aand, therefore, in the region directly under the field plate section,viewed from the gate electrode 5 towards the drain electrode 8, therelative permittivity (the average value) of the dielectric films dropswhen the film thickness thereof increases. Accordingly, the capacitanceof a capacitor that consists of the field plate section and a channellayer 2 separated by a first dielectric film 4 a and a second dielectricfilm 4 b becomes smaller towards the drain electrode 8. Now, referringto FIGS. 6 and 7, a manufacturing method of an FET of the presentexample is described below.

[0099] First, in the same way as First example, upon a semi-insulatingGaAs substrate 1, a layered structure of an N-type GaAs channel layer 2,an N-type GaAs contact layer 3, a first dielectric film 4 a and a gatemetal film 6 is formed, and the superfluous section of the gate metalfilm 6 is removed by ion milling, and thereby a gate electrode 5 isformed (FIG. 6(a)).

[0100] The material for the first dielectric film 4 a is Ta₂O₅ and thefilm thickness thereof is 150 nm.

[0101] Next, a second dielectric film 4 b is deposited over the entiresurface (FIG. 6(b)). The material for the second dielectric film 4 b isSi₃N₄ and the film thickness thereof is 150 nm.

[0102] The entire surface is then subjected to dry etching and thesecond dielectric film 4 b lying on the gate electrode 5 is completelyremoved in substance (FIG. 6(c)).

[0103] Next, a 50 nm-thick TiN film, a 15 nm-thick Pt film and a 400nm-thick Au film are deposited, in this order, over the entire surfaceby sputtering, which forms a gate metal film 6, again, and thereafter,by removing the superfluous section by means of ion milling, a gateelectrode 5 is formed (FIG. 6(d)).

[0104] Next, the first and the second dielectric films 4 a and 4 bformed in the region other than the section where the gate electrode 5is formed are removed by etching. Subsequently, an 8 nm-thick Ni film, a50 nm-thick AuGe film and a 250 nm-thick Au film are successively grownin this order by vacuum deposition and thereby a source electrode 7 anda drain electrode 8 are formed to accomplish an FET (FIG. 7).

[0105] In the FET of the present example, because the dielectric filmsmade of Ta₂O₅ and Si₃N₄, respectively, are formed only in the regiondirectly under the field plate section, excellent gain characteristicscan be obtained while maintaining withstand voltage characteristics.

[0106] Further, the FET of the present example has a structure in whichthe capacitance of the capacitor formed in the section directly underthe field plate section decreases towards the drain electrode 8. Thisarrangement moderates the effects on the field relaxation by the fieldplate section on the drain side and facilitates to achieve an idealfield profile. Therefore, the FET produced has still more excellenthigh-frequency characteristics, together with high withstand voltagecharacteristics.

Fifth Example

[0107] As shown in FIG. 9(f), the FET of the present example has astructure wherein two sorts of dielectric films 4 a and 4 b are formedbetween an overhanging field plate section and a channel layer 2. In theregion directly under the field plate section, viewed from the gateelectrode 5 towards the drain electrode 8, the relative permittivity(the average value) of the dielectric film drops. Accordingly, thecapacitance of a capacitor that consists of the field plate section andthe channel layer 2 becomes smaller. Now, referring to FIGS. 8 and 9, amanufacturing method of an FET of the present example is describedbelow.

[0108] First, in the same way as First example, upon a semi-insulatingGaAs substrate 1, a layered structure of an N-type GaAs channel layer 2and an N-type GaAs contact layer 3 is formed. Next, after a gate metalfilm is deposited over the entire surface, the superfluous portionthereof is removed by ion milling, and thereby a gate electrode 5 isformed (FIG. 8(a)).

[0109] Next, over the entire surface, a first and a second dielectricfilm 4 a and 4 b are deposited (FIG. 8(b)). The material for the firstdielectric film 4 a is Ta₂O₅ and the film thickness thereof is 150 nm.The material for the second dielectric film 4 b is Si₃N₄ and the filmthickness thereof is 150 nm.

[0110] A photoresist is then formed, leaving only a section where a gateelectrode is formed as an opening (FIG. 8(c)). Using this photoresist asa mask, dry etching is applied so as to remove completely in substancethe second dielectric film 4 b lying on the gate electrode 5 (FIG.8(d)).

[0111] Next, a 50 nm-thick TiN film, a 15 nm-thick Pt film and a 400nm-thick Au film are deposited, in this order, over the entire surfaceby sputtering, which forms a gate metal film 6, again, and thereafter,by removing the superfluous section by means of ion milling, a gateelectrode 5 is formed (FIG. 9(e)).

[0112] Next, the first and the second dielectric films 4 a and 4 bformed in the region other than the section where the gate electrode 5is formed are removed by etching. Subsequently, an 8 nm-thick Ni film, a50 nm-thick AuGe film and a 250 nm-thick Au film are successively grownin this order by vacuum deposition and thereby a source electrode 7 anda drain electrode 8 are formed to accomplish an FET (FIG. 9(f)).

[0113] In the FET of the present example, because the dielectric filmsmade of Ta₂O₅ and Si₃N₄, respectively, are formed only in the regiondirectly under the field plate section, excellent gain characteristicscan be obtained while maintaining withstand voltage characteristics.

[0114] Further, the FET of the present example has a structure in whichthe capacitance of the capacitor formed in the section directly underthe field plate section decreases towards the drain electrode 8. Thisarrangement moderates the effects on the field relaxation by the fieldplate section on the drain side and facilitates to achieve an idealfield profile. Therefore, characteristics of withstand voltage can beimproved, while the deterioration of the high-frequency characteristicsis kept down to the minimum.

Sixth Example

[0115] In the present example, as shown in FIG. 10, a gate electrode 5takes a varied shape. FIG. 10 (a) and (b) each show a gate electrode 5with the edge section on the drain side in the shape of a comb and FIG.10 (c) shows a gate electrode 5 with a plurality of openings in the edgesection on the drain side. In any form, the area of electrode S inEquation (1)

C=εS/d  (1)

[0116] (C: the capacitance, ε: the permittivity, S: the area ofelectrode, d: the distance between electrodes is reduced on the drainside and thereby the electrostatic capacitance per unit area directlyunder the gate electrode 5 is made smaller on the drain side than on thegate side. This arrangement moderates the effects on the fieldrelaxation by the field plate section on the drain side and facilitatesto achieve an ideal field profile. Therefore, the FET produced has stillmore excellent high-frequency characteristics, together with highwithstand voltage characteristics.

[0117] Further, the gate electrode can be worked into a varied shapesuch as the one shown in FIG. 10, using known etching techniques.

Seventh Example

[0118] The FET of the present example is provided with a field controlelectrode 11 between a drain electrode 8 and a gate electrode 5, asshown in FIG. 11(a). This arrangement further improves characteristicsof withstand voltage.

[0119] This FET can be produced by forming a field control electrode 11after a gate electrode 5 that has a dielectric film 4 directly under afield plate section is formed, following the same steps as Secondexample. With regard to the field control electrode 11, a 50 nm-thick Tifilm, a 30 nm-thick Pt film and a 200 nm-thick Au film are first grownin succession in this order over the entire surface by vacuumdeposition. Thereafter the superfluous section is removed by ionmilling, and thereby the field control electrode 11 is formed.

Eighth Example

[0120] The FET of the present example is provided with a sub electrode12 between a source electrode 7 and a gate electrode 5, as shown in FIG.11(b).

[0121] This FET can be produced by forming a sub electrode 12 after agate electrode 5 that has a dielectric film 4 directly under a fieldplate section is formed, following the same steps as Second example.With regard to the sub electrode 12, a 50 nm-thick Ti film, a 30nm-thick Pt film and a 200 nm-thick Au film are first grown insuccession in this order over the entire surface by vacuum deposition.Thereafter the superfluous section is removed by ion milling, andthereby the sub electrode 12 is formed.

[0122] The sub electrode 12 is connected, for example, with a drainelectrode, to which a positive voltage is applied. This lowers theresistance of the region directly under the sub electrode 12 and easesthe current flow so that higher efficiency of the element can beattained.

Ninth Example

[0123] The FET of the present example is provided with a float electrode13 under a field plate section 9, as shown in FIG. 13. For this FET,after carrying out the steps of First example up to the step of FIG.1(c) (the dielectric film 4 of FIG. 1 corresponds to a dielectric film 4a of FIG. 13) in the same manner, a metal material to constitute a floatelectrode 13 and then a dielectric film 4 b are deposited. Next, thesection where a gate electrode is to be formed is etched and thereaftera gate metal film 6 is formed over the entire surface. Subsequently, thesame steps as those of First example after FIG. 2(e) are performed andthe FET with a structure shown in FIG. 13 is accomplished. As a materialfor the float electrode, for instance, tungsten silicide (WSi),aluminium, gold, titanium/platinum/gold or the like can be utilized.

[0124] Because the FET of the present example is provided with a floatelectrode as described above, electrons are kept in the float electrodeeven when the applied voltage to the field plate section is switched offand, in consequence, the field centralization on the edge section of thegate electrode on the drain side is relaxed and spread over.

Tenth Example

[0125] In the FET of the present example, as shown in FIG. 16(g), a gateelectrode is provided with an overhanging field plate section 9 and adielectric film 4′ made of SiO₂ is formed between this field platesection 9 and a channel layer 2.

[0126] Referring to FIGS. 15 and 16, a manufacturing method of an FET ofthe present example is described below.

[0127] First, upon a semi-insulating GaAs substrate 1, an N-type GaAschannel layer 2 (with a thickness of 230 nm) doped with 2×10¹⁷ cm⁻³ Siand an N-type GaAs contact layer 3 (with a thickness of 150 nm) dopedwith 5×10¹⁷ cm⁻³ Si are grown in succession by the MBE (Molecular BeamEpitaxy) method (FIG. 15(a)).

[0128] Next, using a resist (not shown in the drawing) as a mask, thechannel layer 2 and the contact layer 3 are etched by wet etching with asulfuric acid based or phosphoric acid based etchant so as to form arecess (FIG. 15 (b)).

[0129] A dielectric film 4′ of SiO₂ is then deposited to a thickness of150 nm over the entire surface by the CVD (Chemical Vapour Deposition)method (FIG. 15(c)). On this dielectric film 4′, a resist (not shown inthe drawing) is formed and, using this as a mask, a portion of thedielectric film 4′ where a gate electrode is to be formed is etched bydry etching with CHF₃ or SF₆. Next, using the dielectric film 4′ as amask, a portion of the channel layer 2 where the gate electrode is to beformed is etched to a depth of 30 nm or so (FIG. 15 (d) ).

[0130] Next, a 100 nm-thick WSi film, a 50 nm-thick TiN film, a 15nm-thick Pt film and a 400 nm-thick Au film are deposited, in thisorder, over the entire surface by sputtering, which forms a gate metalfilm 6 (FIG. 16(e)). After that, a photoresist is applied only to asection thereof where the gate electrode is to be formed, and the othersuperfluous section is removed by ion milling, and thereby a gateelectrode 5 is formed (FIG. 16(f)).

[0131] Following this, the prescribed sections of the dielectric film 4′are etched to expose the contact layer 3 and then an 8 nm-thick Ni film,a 50 nm-thick AuGe film and a 250 nm-thick Au film are successivelygrown in this order by vacuum deposition and thereby a source electrode7 and a drain electrode 8 are formed to accomplish an FET (FIG. 16(g)).

[0132] In the FET of the present example, SiO₂ is utilized as a materialof the dielectric film 4′ between the field plate section and thechannel layer. The relative permittivity of SiO₂ is 3.9 or so and thefilm thickness of the dielectric film 4′ is 150 nm. Thus, the value oft/ε becomes approximately 38 and the following equations (1) and (2) aresatisfied.

1<ε<5  (1)

25<t/ε<70  (2)

[0133] With a dielectric film 4′ that satisfies the above conditions,the FET of the present example shows excellent characteristics ofwithstand voltage and, in addition, has a good protection against thebreakdown of the dielectric film or the generation of the currentleakage.

Eleventh Example

[0134] Apart from using a SiN film as a material of a dielectric film 4′and setting the film thickness thereof 200 nm, an FET is manufactured inthe same way as Tenth example (FIG. 16(g)).

[0135] The relative permittivity of SiN is 7 or so and the filmthickness of the dielectric film 4′ is 200 nm so that the FET of thepresent example satisfies the following equations (1) and (2).

5≦ε<8  (1)

100<t<350  (2)

[0136] Accordingly, the FET of the present example shows excellentcharacteristics of withstand voltage and, in addition, has a goodprotection against the breakdown of the dielectric film or thegeneration of the current leakage.

[0137] The entire disclosure of Japanese Patent ApplicationNo.HEI10-268394 including specification, claims, drawings and summaryare incorporated herein by reference in its entirety.

What is claimed is:
 1. A field effect transistor; comprising asemiconductor substrate with a channel layer being formed on itssurface; a source electrode and a drain electrode being formed at adistance on said semiconductor substrate; and a gate electrode beingplaced between said source electrode and said drain electrode and makinga Schottky junction with said channel layer; wherein: said gateelectrode is provided with an overhanging field plate section; andbetween said field plate section and said channel layer, there is laid adielectric film made of a high dielectric material with a relativepermittivity of 8 or more.
 2. The field effect transistor according toclaim 1, wherein said high dielectric material is a material selectedfrom the group consisting aluminium oxide (Al₂O₃), aluminium nitride,tantalum oxide (Ta₂O₅), strontium titanate (SrTiO₃), barium titanate(BaTiO₃), barium titanate strontium (Ba_(x)Sr_(1-x)TiO₃ (0<x<1)) andbismuth tantalate strontium (SrBi₂Ta₂O₉)
 3. The field effect transistoraccording to claim 1, wherein the surface of said channel layer ispartially or entirely covered with a silicon oxide film and saiddielectric film is laid between said silicon dioxide film and said fieldplate section.
 4. The field effect transistor according to claim 1,wherein the film thickness of said dielectric film is 100 to 1500 nm. 5.The field effect transistor according to claim 1, wherein saiddielectric film is formed only in a region directly under said fieldplate section.
 6. The field effect transistor according to claim 1,wherein the electrostatic capacitance per unit area of a capacitor thatconsists of said field plate section and said channel layer separated bysaid dielectric film decreases with distance from the gate electrode. 7.The field effect transistor according to claim 1, wherein the thicknessof said dielectric film directly under said field plate section is lesson the side of the gate electrode than on the side of the drainelectrode.
 8. The field effect transistor according to claim 1, whereinone or more openings are formed in said field plate section.
 9. Thefield effect transistor according to claim 1, wherein the edge sectionof said field plate section on the side of the drain electrode iscomb-shaped.
 10. The field effect transistor according to claim 1,wherein the permittivity of said dielectric film directly under saidfield plate section decreases with distance from said gate electrode.11. The field effect transistor according to claim 1, wherein a floatelectrode is set under said field plate section.
 12. The field effecttransistor according to claim 1, wherein a field control electrode isset, in addition, over the dielectric film on said channel layer,between said gate electrode and said drain electrode.
 13. The fieldeffect transistor according to claim 1, wherein a sub electrode is set,in addition, over the dielectric film on said channel layer, betweensaid gate electrode and said source electrode.
 14. The field effecttransistor according to claim 1, wherein said channel layer is made of agroup III-V compound semiconductor.
 15. A field effect transistor;comprising: a semiconductor substrate with a channel layer being formedon its surface; a source electrode and a drain electrode being formed ata distance on said semiconductor substrate; and a gate electrode beingplaced between said source electrode and said drain electrode and makinga Schottky junction with said channel layer; wherein: said gateelectrode is provided with an overhanging field plate section; andbetween said field plate section and said channel layer, there is laid adielectric film; and when the relative permittivity and the filmthickness of the dielectric film are denoted by ε and t (nm),respectively, one of the following conditions (1) and (2) is satisfied.1<ε<5, and 25<t/ε<70  (1)5=ε<8, and 100<t<350  (2)
 16. The field effecttransistor according to claim 15, wherein said dielectric film is formedonly in a region directly under said field plate section.
 17. The fieldeffect transistor according to claim 15, wherein the electrostaticcapacitance per unit area of a capacitor that consists of said fieldplate section and said channel layer separated by said dielectric filmdecreases with distance from the gate electrode.
 18. The field effecttransistor according to claim 15, wherein the thickness of saiddielectric film directly under said field plate section is less on theside of the gate electrode than on the side of the drain electrode. 19.The field effect transistor according to claim 15, wherein one or moreopenings are formed in said field plate section.
 20. The field effecttransistor according to claim 15, wherein the edge section of said fieldplate section on the side of the drain electrode is comb-shaped.
 21. Thefield effect transistor according to claim 15, wherein the permittivityof said dielectric film directly under said field plate sectiondecreases with distance from said gate electrode.
 22. The field effecttransistor according to claim 15, wherein a float electrode is set undersaid field plate section.
 23. The field effect transistor according toclaim 15, wherein a field control electrode is set, in addition, overthe dielectric film on said channel layer, between said gate electrodeand said drain electrode.
 24. The field effect transistor according toclaim 15, wherein a sub electrode is set, in addition, over thedielectric film on said channel layer, between said gate electrode andsaid source electrode.
 25. The field effect transistor according toclaim 15, wherein said channel layer is made of a group III-V compoundsemiconductor.